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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 1999-2006, zarlink semiconductor inc. all rights reserved. features ? single 2.7-3.6 volt supply operation ? mt91l61 version features a delayed framing pulse in ssi and st-bus modes to facilitate cascaded devices ? programmable -law/a-law codec and filters ? programmable itu-t (g.711)/sign-magnitude coding ? programmable transmit, receive and side-tone gains ? fully differential interface to handset transducers - including 300 ohm receiver driver ? flexible digital interface including st-bus/ssi ? serial microport ? low power operation ? itu-t g.714 compliant ? multiple power down modes applications ? battery operated equipment ? digital telephone sets ? cellular radio sets ? local area communications stations ? pair gain systems ? line cards march 2006 ordering information mt91l61ae 24 pin pdip tubes mt91l60ae 24 pin pdip tubes mt91l61as 24 pin soic tubes mt91l60as 20 pin soic tubes mt91l61an 24 pin ssop tubes mt91l60an 20 pin ssop tubes MT91L60ASR 20 pin soic tape & reel mt91l61asr 24 pin soic tape & reel mt91l61asr1 24 pin soic* tape & reel mt9160an1 20 pin ssop* tubes *pb free matte tin -40 c to +85 c iso 2 -cmos mt91l60/61 3 volt multi-featured codec (mfc) data sheet figure 1 - functional block diagram m - m + hspkr + hspkr - filter/codec gain encoder decoder 7db -7db transducer interface flexible digital interface timing st-bus c & d channels serial microport a/ /irq vssd vdd vssa vbias vref din dout stb/f0i clockin pwrst ic cs data1 data2 sclk stbd/food (mt91l61only)
mt91l60/61 data sheet 2 zarlink semiconductor inc. description the mt91l60/61 3 v multi-featured codec incorporates a built- in filter/codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, refe rence voltage and bias source. the device supports both itu- t and sign- magnitude a-law and -law requirements. the mt91l60/61 is a true 3 v device employing a fully differential architecture to ensure wide dynamic range. complete telephony interfaces are provided for connect ion to handset transducers. internal register access is provided through a serial microport compatible with various industry standard micro-controllers. the mt91l60/61 is fabricated in zarlink's iso 2 -cmos technology ensuring low power consumption and high reliability.
mt91l60/61 data sheet 3 zarlink semiconductor inc. figure 2 - pin connections pin description pin # 20 pin24 pin name description 11v bias bias voltage (output). (v dd /2) volts is available at this pin for biasing external amplifiers. connect 0.1 f capacitor to v ssa . 22v ref reference voltage for codec (output). used internally. nomi nally [vdd/2 - 1.1] volts. connect 0.1 f capacitor to v ssa . 34pwrst power-up reset (input). cmos compatible input with schmitt trigger (active low). 45 ic internal connection. tie externally to v ssd for normal operation. 56a/ /irq a/ - when internal control bit den = 0 this cmos level compatible input pin governs the companding law used by the filter/codec; -law when tied to v ssd and a-law when tied to v dd . logically or?ed with a/ register bit. irq - when internal control bit den = 1 th is pin becomes an open-drain interrupt output signalling valid access to t he d-channel registers in st-bus mode. 67v ssd digital ground. nominally 0 volts. 78cs chip select (input). this input signal is used to select the device for microport data transfers. active low. cmos level compatible. 810sclk serial port synchronous clock (input). data clock for microport. cmos level compatible. 911data 1 bidirectional serial data. port for microprocessor serial data transfer. in motorola/national mode of operation, this pin becomes the data transmit pin only and data receive is performed on the data 2 pin. input cmos level compatible. 10 12 data 2 serial data receive. in motorola/national mode of operation, this pin is used for data receive. in intel mode, serial data transmit and receive are performed on the data 1 pin and data 2 is disconnected. input cmos level compatible. 11 13 d out data output. a high impedance three-state digita l output for 8 bit wide channel data being sent to the layer 1 transceiver. da ta is shifted out via this pin concurrent with the rising edge of the bit clock during th e timeslot defined by stb, or according to standard st-bus timing. m - m + vbias vref ic vssd sclk data1 data2 din dout vssa hspkr + hspkr - vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 nc pwrst a/ /irq cs nc stb/f0i nc clockin nc m - m + vbias vref ic vssd sclk data1 data2 din dout vssa hspkr + hspkr - vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 pwrst a/ /irq cs stb/f0i clockin 20 pin soic/ssop 24 pin pdip m - m + vbias vref ic vssd sclk data1 data2 din dout vssa hspkr + hspkr - vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 nc pwrst a/ /irq cs nc stb/f0i stbd/food clockin nc 24 pin pdip/soic/ssop mt91l60as/an mt91l60ae mt91l61ae/as/an
mt91l60/61 data sheet 4 zarlink semiconductor inc. overview the 3 v multi-featured codec (mfc) features complete an alog/digital and digital/analog conversion of audio signals (filter/codec) and an analog interface to a standard handset transmitter and receiver (transducer interface). the receiver amplifier is capable of driving a 300 ohm load. each of the programmable parameters wi thin the functional blocks is accessed through a serial microcontroller port compatible with intel mcs-51 ? , motorola spi ? and national semiconductor microwire ? specifications. these parameters include: gain control, power down, mute, b-channel select (st-bus mode), c&d channel control/access, law control, digital interface programming and loopback. opti onally the device may be used in a controllerless mode utilizing the power-on default settings. 12 14 d in data input. a digital input for 8 bit wide channel data received from the layer 1 transceiver. data is sampled on the falling edge of the bit clock during the timeslot defined by stb, or according to standar d st-bus timing. input level is cmos compatible. 13 15 stb/f0i data strobe/frame pulse (input). for ssi mode this input determines the 8 bit timeslot used by the device for both tran smit and receive data. this active high signal has a repetition rate of 8 khz. st andard frame pulse definitions apply in st- bus mode. cmos level compatible input. 16 stbd/f0 od (mt91l6 1 only) delayed frame pulse output . in ssi mode, an 8 bit wide strobe is output after the first strobe goes low. in st-bus mode, a frame pulse is output after 4 channel timeslots. 14 17 clockin clock (input). the clock provided to this input pi n is used for the internal device functions. for ssi mode connect the bit cloc k to this pin when it is 512 khz or greater. connect a 4096 khz clock to this input when the available bit clock is 128 khz or 256 khz. for st-bus mode connect c4i to this pin. cmos level compatible. 15 18 v dd positive power supply (input). nominally 3 volts. 16 19 hspkr- inverting handset speaker (output). output to the handset speaker (balanced). 17 20 hspkr+ non-inverting handset speaker (output). output to the handset speaker (balanced). 18 22 v ssa analog ground (input). nominally 0 volts. 19 23 m- inverting microphone (input). inverting input to mi crophone amplifier from the handset microphone. 20 24 m+ non-inverting microphone (input). non-inverting input to microphone amplifier from the handset microphone. 3,9, 16,21 nc no connect . (24 packages only). pin 16 is nc for mt91l60. pin description (continued) pin # 20 pin24 pin name description
mt91l60/61 data sheet 5 zarlink semiconductor inc. functional description filter/codec the filter/codec block implements conversion of the analog 0-3.3 khz speech signals to/from the digital domain compatible with 64 kb/s pcm b-channels. selection of companding curves and digital code assignment are programmable. these are itu-t g.711 a-law or -law, with true-sign/alternate di git inversion or true-sign/inverted magnitude coding, respectively. optionally, sign-m agnitude coding may also be selected for proprietary applications. the filter/codec block also implements transmit and receive audio path gains in the analog domain. a programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. this side tone path feature is disabl ed by default. figure 3 depicts the nominal half-channel and side-tone gains for the mt91l60/61. in the event of pwrst , the mt91l60/61 defaults such that the side-tone path is off, all programmable gains are set to 0db and itu-t -law is selected. further, the digital port is se t to ssi mode operation at 2048 kb/s and the fdi and driver sections are powered up. (see microport section.) the internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 3 volt supply design. this fully differen tial architecture is continued into the transducer interface section to provide full chip realization of these capabi lities for the handset functions. a reference voltage (v ref ), for the conversion requirements of the codec section, and a bias voltage (v bias ), for biasing the internal analog sect ions, are both generated on-chip. v bias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. a 0.1 f capacitor must be connected from v bias to analog ground at all times. although v ref may only be used internally, a 0.1 f capacitor must be connected from v ref to ground. the analog ground reference point for these two capa citors must be physically t he same point. to facilitate this the v ref and v bias pins are situat ed on adjacent pins. the transmit filter is designed to meet itu-t g.714 specif ications. the nominal gain fo r this filter is 0 db (gain control = 0 db). gain control allows the output signal to be increased up to 7 db. an anti-aliasing filter is included. this is a second order lowpass implement ation with a corner frequency at 25 khz. the receive filter is designed to meet itu-t g.714 specifications. the nominal gain for this filter is 0 db (gain control = 0 db). gain control allows the output signal to be atten uated up to 7 db. filter response is peaked to compensate for the sinx/x attenuation caused by the 8 khz sampling rate. side-tone is derived from the in put of the tx filter and is not subject to t he gain control of the tx filter section. side- tone is summed into the receive handset tr ansducer driver path after the rx fi lter gain control section so that rx gain adjustment will not affect side-tone levels. the side -tone path may be enabled/di sabled with the gain control bits located in gain control register 2 (address 01h). transmit and receive filter gains are controlled by the txfg 0 -txfg 2 and rxfg 0 -rxfg 2 control bits, respectively. these are located in gain control regi ster 1 (address 00h). transmit filter gain is adjustable from 0db to +7db and receive filter gain from 0db to -7db, both in 1db increments. side-tone filter gain is controlled by the stg 0 -stg 2 control bits located in gain control register 2 (address 01h). side-tone gain is adjustable from -9.96 db to +9.96 db in 3.32 db increments. companding law selection for the filter/codec is provided by the a/ companding control bit while the coding scheme is controlled by the smag/itu-t control bit. the a/ control bit is logically or?ed with the a/ pin providing access in both controller and controllerless modes. both a/ and smag/itu-t reside in control register 2 (address 04h). table 1 illustrates these choices.
mt91l60/61 data sheet 6 zarlink semiconductor inc. table 1 transducer interfaces standard handset transducer interfaces are provided by the mt91l60/61. these are: ? the handset microphone inputs (transmitter), pins m+ /m-. the nominal transmit path gain may be adjusted to either 6.0 db or 15.3 db. control of this gain is provided by the txinc control bit (gain control register 1, address 00h). ? the handset speaker outputs (receiver), pins hspkr+/hspkr-.this internally compensated fully differential output driver is capable of driving the l oad shown in figure 3. the nominal receive path gain may be adjusted to either 0 db, -6 db or -12 db. control of this gain is provided by the rxinc control bit (gain control register 1, address 00h). this gain adjustment is in addition to the programmable gain provided by the receive filter. figure 3 - audio gain partitioning code sign/ magnitude itu-t (g.711) -law a-law + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 -zero (quiet code) 0000 0000 0111 1111 0101 0101 - full scale 0111 1111 0000 0000 0010 1010 serial port filter/codec and transducer interface handset receiver (150 ? ) pcm receive filter gain 0 to -7 db (1 db steps) side-tone -9.96 to +9. 96 db -11 db (3.32 db steps) -6 db receiver driver -6.0 db or 0 db hspkr + hspkr - 75 ? internal to device external to device default bypass m+ m - transmit gain 6.37 db transmit gain -0.37 db or 8.93 db gain 0 to +7 db pcm transmitter microphone d in d out transmit filter gain 0 to +7 db (1 db steps) 75 ? default side-tone off decoder encoder
mt91l60/61 data sheet 7 zarlink semiconductor inc. microport the serial microport, compatible with intel mcs-51 (mode 0), motorola spi (cpol=0,cpha=0) and national semiconductor microwire specifications provides access to all mt91l60/61 in ternal read and write registers. this microport consists of a transmit/receive data pin (data1 ), a receive data pin (data2), a chip select pin (cs ) and a synchronous data clock pin (sclk). for d-channel contention control, in st-b us mode, this interface provides an open-drain interrupt output (irq ). the microport dynamically senses the st ate of the serial clock (sclk) each time chip select becomes active. the device then automatically adjusts its internal timing and pin configuration to conform to intel or motorola/national requirements. if sclk is high during chip select activati on then intel mode 0 timing is assumed. the data1 pin is defined as a bi-directional (transmit/rece ive) serial port and data2 is internally disconnected. if sclk is low during chip select activation then motorola/national timing is assumed. motorola processor mode cpol=0, cpha=0 must be used. data1 is defined as the data transmit pin while data2 becomes the data receive pin. although the dual port motorola controller configuration usually supports full-duplex communication, onl y half-duplex communication is possible in the mt91l60/61. the micr o must discard non-valid data which it clocks in during a valid write transfer to the mt91l60/61. during a valid read tr ansfer from the mt91l60/61 data simu ltaneously clocked out by the micro is ignored by the mt91l60/61. all data transfers through the micropor t are two-byte transfers requiring the transmission of a command/address byte followed by the data byte writte n or read from the addressed register. cs must remain asserted for the duration of this two-byte transfer. as shown in figures 5 and 6 the falling edge of cs indicates to the mt91l60/61 that a microport transfer is about to begin. the first 8 clock cycles of sclk after the falling edge of cs are always used to receive the command/address byte from the microcontroller. the command/address byte contains information detailing whether the second byte transfer will be a read or a write operation and at wh at address. the next 8 clock cycles are used to transfer the data byte between the mt91l60/61 and the microcontroller. at the end of the two-byte transfer cs is brought high again to terminate the session. the rising edge of cs will tri-state the output driver of data1 which will remain tri-stated as long as cs is high. intel processors utilize least signific ant bit first transmission while moto rola/national processors employ most significant bit first transmission. the mt91l60/61 microport automatically accommodates these two schemes for normal data bytes. however, to ensure decoding of the r/w and address information, the command/address byte is defined differently for intel operation than it is for motorola/national operation. refer to the relative timing diagrams of figures 5 and 6. receive data is sampled on the rising edge of sclk while transmit data is made available concurrent with the falling edge of sclk.
mt91l60/61 data sheet 8 zarlink semiconductor inc. figure 4 - audio gain partitioning figure 5 - serial port relative timing fo r motorola mode 00/national microwire d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 xx a 2 a 1 a 0 r/w d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1) delays due to internal processor timing which are transparent. 2) the mt91l60/l61:latches received data on the rising edge of sclk. 3) the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the 4) a new command/address byte may be loaded only by cs cycling high then low again. 5) the command/address byte contains: 1) 3) 4) 5) 1) 2) 3) 4) command/address data input/output command/address: data 1 receive data 1 transmit sclk cs d 7 d 0 -outputs transmit data on the falling edge of sclk. subsequent byte is always data until terminated via cs returning high. 1 bit - read/write 3 bits - addressing data 4 bits - unused xx d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1) 3) 4) 1) 2) 3) 4) command/address data input/output command/address: data 2 receive data 1 transmit sclk cs r/w xa 1 a 0 x d 7 d 0 1) delays due to internal proce ssor timing which are transparent. 3) the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the 4) a new command/address byte may be loaded only by cs cycling high then low again. 5) the command/address byte contains: subsequent byte is always data until terminated via cs returning high. 1 bit - read/write 3 bits - addressing data 4 bits - unused 5) 2) the mt91l60/l61: latches received data on the rising edge of sclk. -outputs transmit data on the falling edge of sclk. xx a 2
mt91l60/61 data sheet 9 zarlink semiconductor inc. flexible digital interface a serial link is required to transport data between t he mt91l60/61 and an external digi tal transmission device. the mt91l60/61 utilizes the st-bus architecture defined by zarlink semiconductor but also supports a strobed data interface found on many standard codec devices. this interfac e is commonly referred to as simple serial interface (ssi). the combination of st-bus and ssi provides a flexible digital inte rface (fdi) capable of supporting all zarlink basic rate transmission devices as well as many other 2b+d transceivers. the required mode of operation is select ed via the csl2-0 control bits (cont rol register 2, address 04h). pin definitions alter dependent upon the oper ational mode selected, as described in the following subsections as well as in the pin description tables. quiet code the fdi can be made to send quiet code to the decoder and receive filter path by setting the rxmute bit high. likewise, the fdi will send quiet code in the transmit path when the txmute bi t is high. both of these control bits reside in control register 1 at address 03h. when either of these bits are low thei r respective paths function normally. the -zero entry of table 1 is used for the quiet code definition. st-bus mode the st-bus consists of output (dsto) and input (dsti) se rial data streams, in fdi these are named dout and din respectively, a synchronous clock input signal clockin (c4i ), and a framing pulse input (f0i ). these signals are direct connections to the corresponding pins of zarlink basic rate devices. the csl2, csl1 and csl0 bits are set to 1 for st-bus operation. the data streams operate at 2048 kb/s and are time di vision multiplexed into 32 identical channels of 64 kb/s bandwidth. a frame pulse (a 244 nsec low going pulse) is used to separate the continuous serial data streams into the 32 channel tdm frames. each frame has a 125 second period translating into an 8 khz frame rate. a valid frame begins when f0i is logic low coincident with a falling edge of c4i . refer to figure 11 for detailed st-bus timing. c4i has a frequency (4096 khz) which is twice the data rate . this clock is used to sample the data at the 3/4 bit-cell position on dsti and to make data availa ble on dsto at the start of the bit-cell. c4i is also used to clock the mt91l60/61 internal functions (i.e., filter/codec, digita l gain and tone generation) and to provide the channel timing requirements. the mt91l60/61 uses only the first four channels of the 32 channel frame. these c hannels are always defined, beginning with channel 0 after the frame pulse, as sh own in figure 6 (st-bus channel assignments). the mt91l60/61 provides a delayed frame pulse (f0od ), 4 channels after the input frame pulse. the first two (d & c) channels are enabled for use by the den and cen bits respectively, (control register 2, address 04h). isdn basic rate service (2b+d) defines a 16 kb/s signalling (d) channel. the mt91l60/61 supports transparent access to this signalling channel. st-bus basic rate transmission devices, which may not employ a microport, provide access to their inte rnal control/status registers through the st-bus control (c) channel. the mt91l60/61 supports microport access to this c-channel. figure 6 - st-bus channel assignment f0i dsti, dsto lsb first for d- channel msb first for c, b1- & b2- channels channel 0 d-channel channel 1 c-channel channel 2 b1-channel channel 3 b2-channel channels 4-31 not used 125 s food
mt91l60/61 data sheet 10 zarlink semiconductor inc. den - d-channel in st-bus mode access to the d-channel (transmit and re ceive) data is provided through an 8-bit read/write register (address 06h). d-chan nel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame for 16 kb/s operation (1 bit/frame for 8 kb/s operation). since the st-bus is asynchronous, with respect to the microport, valid access to this register is controlled through the us e of an interrupt (irq ) output. d-channel access is enabled via the (den) bit. den: when 1, st-bus d-channel data (1 or 2 bits/frame depending on the state of the d8 bit) is shifted into/out of the d- channel (read/write) register. when 0, the receive d-channel data (read) is still shif ted into the proper register while the dsto d-channel timeslot and irq outputs are tri-stated (default). d8: when 1, d-channel data is shifted at the rate of 1 bit/frame (8 kb/s). when 0, d-channel data is shifted at th e rate of 2 bits/frame (16 kb/s default). 16 kb/s d-channel operation is the default mode which allo ws the microprocessor access to a full byte of d- channel information every fourth st-bus frame. by arbitrarily assigning st-bus frame n as the reference frame, during which the microprocesso r d-channel read and write operations are performed, then: a. a microport read of address 04 hex will result in a byte of data being extracted which is composed of four i-bits (designated by roman numeral s i,ii,iii,iv). these di-bits are com posed of the two d-channel bits received during each of frames n, n-1, n-2 and n-3. re ferring to fig. 7a: di-bit i is mapped from frame n- 3, di-bit ii is mapped from frame n-2, di-bit iii is mapped from frame n-1 and di-bit iv is mapped from frame n. the d-channel read register is not preset to any particular value on power-up (pwrst ) or software reset (rst). b. a microport write to address 04 hex will result in a byte of data being loaded which is composed of four di-bits (designated by roman numerals i, ii, iii, iv). these di-bits are destined fo r the two d-channel bits transmitted during each of frames n+1, n+2, n+3, n+4. referring to fig. 7a: di-bit i is mapped to frame n+1, di-bit ii is mapped to frame n+2, di bit iii is mapped to frame n+3 and di bit iv is mapped to frame n+4. if no new data is written to addr ess 04 hex, the current d- channel register contents will be continuously re- transmitted. the d-channel write register is preset to all ones on power-up (pwrst ) or software reset (rst). an interrupt output is provided (irq ) to synchronize microprocessor access to the d-channel register during valid st-bus periods only. irq will occur every fourth (eighth in 8 kb/s mo de) st-bus frame at the beginning of the third (second in 8 kb/s mode) st-bus bit cell period. the in terrupt will be removed follo wing a microprocessor read or write of address 04 hex or upon enc ountering the following frames f0i input, whichever occurs first. to ensure d- channel data integrity, microport read/write access to a ddress 04 hex must occur before the following frame pulse. see figure 7b for timing. 8 kb/s operation expands the interrupt to every eigh t frames and processes data one-bit-per-frame. d-channel register data is mapped according to figure 7c. cen - c-channel channel 1 conveys the control/status in formation for the layer 1 transceiver . c-channel data is transferred msb first on the st-bus by the mt91l60/61. the full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. consult the data sheet for the selected transceiver for its c-channel bit definitions and order of bit transfer.
mt91l60/61 data sheet 11 zarlink semiconductor inc. when cen is high, data written to the c-channel register (address 05h) is transmitted, most significant bit first, on dsto. on power-up reset (pwrst ) or software reset (rst, address 03h) all c-channel bits default to logic high. receive c-channel data (dsti) is always routed to the r ead register regardless of this control bit's logic state. when low, data transmission is halted and this timeslot is tr i-stated on dsto. b1-channel and b2-channel channels 2 and 3 are the b1 and b2 channels, respectively . b-channel pcm associated with the filter/codec and transducer audio paths is selected on an independent basis for the transmit and receive paths. txbsel and rxbsel (control register 1, address 0 3h) are used for this purpose. if no valid transmit path has been selected then the time slot output on dsto is tri-stated (see pdfdi and pddr control bits, control register 1 address 03h). figure 7a - d-channel 16 kb/s operation figure 7b - irq timing diagram n-3 n-2 n-1 n n+1 n+2 n+3 n+4* microport read/write access d0 d1 i d2 d3 ii d4 d5 iii d6 d7 iv d0 d1 i d2 d3 ii d4 d5 iii d6 d7 iv di-bit group transmit d-channel no preset value power-up reset to 1111 1111 * note that frame n+4 is equivale nt to frame n of the next cycle. irq fp dsto/ dsti di-bit group receive d-channel microport read/write access t ir =500 nsec max r pullup = 10 k t if =500 nsec max d0 d1 reset coincident with read/write of address 04 hex or next fp , whichever occurs first fp c4i c2 irq 8 kb/s operation 16 kb/s operation dsto/ dsti
mt91l60/61 data sheet 12 zarlink semiconductor inc. figure 7c - d-channel 8 kb/s operation ssi mode the ssi bus consists of input and output serial data streams named din and dout respectively, a clock input signal (clockin), and a framing strobe input (stb). the frame strobe must be synchronous with, and eight cycles of, the bit clock. a 4.096 mhz master cl ock is also required for ssi operation if the bit clock is less than 512 khz. the timing requirements for ssi are shown in figures 12 & 13. in ssi mode the mt91l60/61 supports only b-channel oper ation. the internal c and d channel registers used in st-bus mode are not functional for ssi operation. the co ntrol bits txbsel and rxbsel, as described in the st- bus section, are ignored since the b- channel timeslot is defined by the i nput stb strobe. hence, in ssi mode transmit and receive b-channel data are al ways in the channel defined by the stb input. the data strobe input stb determines t he 8-bit timeslot used by the device for both transmit and receive data. this is an active high signal with an 8 kh z repetition rate. the mt91l61 provides a delayed strobe pulse which occurs after the initial strobe goes low and is he ld high for the durat ion of 8 pcm bits. ssi operation is separated into two categories based upon the data rate of the available bit clock. if the bit clock is 512 khz or greater then it is used directly by the inte rnal mt91l60/61 functions allo wing synchronous operation. if the available bit clock is 128 khz or 256 khz, then a 4096 khz master clock is required to derive clocks for the internal mt91l60/61 functions. applications where bit clock (bcl) is below 512 kh z are designated as asynchro nous. the mt91l60/61 will re- align its internal clocks to allow operation when the exter nal master and bit clocks are asynchronous. control bits csl2, csl1 and csl0 in control register 2 (address 04h) are used to program the bit rates. for synchronous operation data is sampled, from din, on the falling edge of bcl during the time slot defined by the stb input. data is made available, on dout, on the rising edge of bcl during t he time slot defined by the stb input. dout is tri-stated at all times when stb is not true. if stb is valid and pddr is set, then quiet code will be transmitted on dout during the valid strobe period. ther e is no frame delay through the fdi circuit for synchronous operation. for asynchronous operation dout and din are as defined fo r synchronous operation except that the allowed output jitter on dout is larger. this is due to the resynchronization circuitry activity and will no t affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively larg e. there is a one frame delay through the fdi circuit for asynchronous operation. refer to the specifications of figures 12 & 13 for both synchronous and asynchronous ssi timing. n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 ii d1 iii d2 iv d3 v d4 vi d5 vii d6 viii d7 i d0 ii d1 iii d2 iv d3 v d4 vi d5 vii d6 viii d7 i d0 no preset value di-bit group receive d-channel power-up reset to 1111 1111 irq fp microport read/write access d-channel di-bit group transmit d-channel
mt91l60/61 data sheet 13 zarlink semiconductor inc. pwrst /software reset (rst) while the mt91l60/61 is held in pwrst no device control or functionality is possible. while in software reset (rst=1, address 03h) only the microport is functional. softwa re reset can only be removed by writing the rst bit low or by performing a hardware pwrst . while the rst bit is high, the other bits in control register 1 are held low and cannot be reprogrammed. therefore to modify control register 1 the rst bit must first be written low, followed by a 2nd write operation which writes the desired data. this av oids a race condition betwe en clearing the reset bit and the writing of the other bits in control register 1. after a power-up reset (pwrst ) or software reset (rst) all control bits assume their "power reset value" default states; -law coding, 0 db rx and 6db tx gains and the devic e powered up in ssi mode 2048 kb/s operation with dout tri-stated while there is no strobe active on stb. if a valid strobe is supplied to stb, then dout will be active, during the defined channel. to attain complete power-down from a normal operatin g condition, write pdfdi = 1 and pddr = 1 (control register 1, address 03h) or set the pwrst pin low. table 2 - 3v multi-featured codec register map note: bits marked "-" are reserved bits and should be written with logic "0" 00 rxinc rxfg 2 rxfg 1 rxfg 0 txinc txfg 2 txfg 1 txfg 0 gain control register 1 01-----stg 2 stg 1 stg 0 gain control register 2 02-------drgainpath control 03 pdfdi pddr rst - t x mute r x mute t x bsel r x bsel control register 1 04 cen den d8 a/ smag/ itu-t csl 2 csl 1 csl 0 control register 2 05 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c-channel register 06 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d-channel register 07----pcm/ analog loopen - - loop back
mt91l60/61 data sheet 14 zarlink semiconductor inc. applications figure 8 shows an application in a wireless phone set. figure 9 shows an mt9161b?s delayed frame pulse driving a second mt9161b. this configuration would be used where multiple codec?s were using a data bus (an example being zarlink?s st-bus). figure 8 - wireless phone set 0.1 f 0.1 f vbias +3v 75 ? 150 ? 75 ? +3v dout din 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 frame pulse clock vbias + - +3v 330 ? + 10 f av = 1 + 2r t t 100k vbias 511 ? electret microphone - + 100k 0.1 f 511 ? + a/ /irq mt91l60 m+ m+ m- r r m- 0.1 f sclk data1 data2 data2 motorola mode only cs intel mcs-51 or motorola spi micro- controller + - m+ r t +3v 330 ? + 10 f electret microphone 1k + 0.1 f m- vbias differential amplifier single-ended amplifier typical external gain av= 5-10 () 3v wireless phone baseband processer 0.1 f 100k
mt91l60/61 data sheet 15 zarlink semiconductor inc. figure 9 - delayed frame pulse of first mt91l61 signalling second mt91l61 0.1 f 0.1 f vbias +3v 75 ? 150 ? 75 ? +3v dout din 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 frame pulse clock a/ /irq mt91l61 m+ m- sclk data1 data2 data2 motorola mode only cs intel mcs-51 or motorola spi micro- controller typical external gain av = 5 - 1 0 () 0.1 f 0.1 f vbias +3v 75 ? 150 ? 75 ? +3v a/ /irq m+ m- sclk data1 data2 data2 motorola mode only cs 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 mt91l61 21 22 23 24 3v timing from pc bus 0.1 f 100k
mt91l60/61 data sheet 16 zarlink semiconductor inc. register summary note: bits marked "-" are reserved bits and should be written with logic "0" receive gain setting (db) rxfg 2 rxfg 1 rxfg 0 transmit gain setting (db) txfg 2 txfg 1 txfg 0 (default) 0 -1 -2 -3 -4 -5 -6 -7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 (default) 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 gain control register 1 address = 00h write/read verify power reset value 1000 0000 76543210 rxinc rxfg 2 rxfg 1 rxfg 0 txfg 2 txfg 1 txfg 0 txinc rxfg n = receive filter gain bit n txfg n = transmit filter gain bit n rxinc: when high, the receive path nominal gain is set to 0 db. when low, this gain is -6.0 db. txinc: when high, the transmit path nominal gain is set to 15.3 db. when low, this gain is 6.0 db. side-tone gain setting (db) stg 2 stg 1 stg 0 (default) off -9.96 -6.64 -3.32 0 3.32 6.64 9.96 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 gain control register 2 address = 01h write/read verify power reset value xxxx x000 76543210 ---- stg 2 stg 1 stg 0 - stg n = side-tone gain bit n
mt91l60/61 data sheet 17 zarlink semiconductor inc. note: bits marked "-" are reserved bits and should be written with logic "0" drgain when high, the receive path is summed with the side tone path and is attenuated by 6db. when low, the receive path cont ains no side tone (default). path control address = 02h write/read verify power reset value xx00 0000 76543210 --- - -- drgain - pdfdi when high, the fdi pla and the filter/codec are po wered down (default). when low, the fdi is active. pddr when high, the ear driver and filter/c odec are powered down (default). in addition, in st-bus mode, the selected output cha nnel is tri-stated. in ssi mode the pcm output code will be -zero code during the valid strobe period. the output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. when low, the driver and filter/codec are active if pdfdi is low. rst when high, a software reset occurs performing the same function as the hardware reset (pwrst ) except that the rst bit remains high and device remains powered up. a software reset can be removed only by writing this bit low or by means of a hardware rese t (pwrst ). this bit is useful for quickly programming the registers to the default power reset values. when this bit is low, the reset condition is removed allowing the registers to be modified txmute when high the transmit pcm stream is in terrupted and replaced with quiet code; thus forcing the output code into a mute s tate (only the output code is muted, the transmit microphone and tr ansmit filter/codec are still func tional). when low the full tran smit path functions normally (default). rxmute when high the received pcm stream is interrupted and replaced with quiet code; thus forcing the receive path into a mute state. when low the full receive path functions normally (default). txbsel when high, the transmit b2 channel is functional in st-bus mo de. when low, the transmit b1 channel is functional in st-bu s mode. not used in ssi mode. rxbsel when high, the receive b2 channel is functional in st-bus mode. when low, the receive b1 channel is functional in st-bus control register 1 address = 03h write/read verify power reset value 0000 0000 76543210 pdfdi pddr txbsel rxbsel rst _ txmute rxmute
mt91l60/61 data sheet 18 zarlink semiconductor inc. note: bits marked "-" are reserved bits and should be written with logic "0" cen when high, data written into the c-channel register (address 05h) is transmitted during channel 1 on dsto. when low, the channel 1 timeslot is tri-stated on dsto . channel 1 data received on dsti is read via the c-channel register (address 05h) regardless of the state of cen. this control bit has significan ce only for st-bus operation an d is ignored for ssi operation. den when high, data written into the d-channel register (address 06h) is transmitted (2 bits/frame) during channel 0 on dsto. the remaining six bits of the d-channel carry no information. when low, the channel 0 timeslot is completely tri-stated on dsto. channel 0 data received on dsti is read via the d-channel register regardless of the stat e of den. this control bit has significance only for st-bus mode and is ignored for ssi operation. d8 when high, d-channel operates at 8 kb/s. when low, d-channel operates at 16 kb/s (default). a/ when high, a-law encoding/decoding is se lected for the mt91l60/61. when low, -law encoding/decoding is selected. smag/itu-t when high, sign-magnitude code assignmen t is selected for the codec input/outpu t. when low, itu-t code assignment is selected for the codec input/output; true sign, inverted magnitude ( -law) or true sign, alternate digit inversion (a-law). csl 2 csl 1 csl 0 bit clock rate (khz) clockin (khz) mode 1 1 1 n/a 4096 st-bus 1 0 0 128 4096 ssi 1 0 1 256 4096 ssi 0 0 0 512 512 ssi 0 0 1 1536 1536 ssi 0 1 0 2048 2048 ssi (default) 0 1 1 4096 4096 ssi control register 2 address = 04h write/read verify power reset value 0000 0010 76543210 cen den csl 1 csl 0 d8 a/ csl 2 smag/ itu-t
mt91l60/61 data sheet 19 zarlink semiconductor inc. note: bits marked "-" are reserved bits and should be written with logic "0" figure 10 - loopback signal flow c-channel register address = 05h write/read power reset value 1111 1111- write 76543210 c7 c6 c5 c4 c2 c1 c0 c3 micro-port access to the st-bus c- channel information read and write xxxx xxxx - read d7-d0 data written to this register will be transmitted every fram e, in channel 0, if the den c ontrol bit is set (address 04h). received d- channel data is valid, regardless of the state of den. these b its are valid for st-bus mode on ly and are accessible only when i rq indicates valid access. d-channel register address = 06h write/read power reset value 1111 1111- write 76543210 d7 d6 d5 d4 d2 d1 d0 d3 xxxx xxxx - read pcm/analog this control bit functions only when loopen is set high. it is ignored when loopen is low. for loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. data on din i s looped back to dout without conversion to the analog do main. however, the receive d/a path (from din to hspkr ) still functions. when low, the device is configured for analog-to-analog operation. an analog input signal at m is looped back to the spkr outputs through the a/d and d/a circuits as well as through the normal transmit a/d path (from m to dout). loopen when high, loopback operation is enabled and the loopback type is governed by the state of the pcm/analog bit. when low, loopbacks are disabled, the device op erates normally and the pcm/analog bit is ignored. loopback register address = 07h write/read verify power reset value xxxx 0000 76543210 -- -- - pcm/ loopen - analog dout m +/- hspkr +/- dout din hspkr +/- analog loopback digital loopback pcm/analog = 0 loopen = 1 pcm/analog = 1 loopen = 1
mt91l60/61 data sheet 20 zarlink semiconductor inc. ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note 1: power delivered to the load is in addition to the bias current requirements. absolute maximum ratings ? parameter symbol min. max. units 1 supply voltage v dd - v ss - 0.3 5 v 2 voltage on any i/o pin v i /v o v ss - 0.3 v dd + 0.3 v 3 current on any i/o pin (transducers excluded) i i /i o 20 ma 4 storage temperature t s - 65 + 150 c 5 power dissipation (package) p d 750 mw recommended operating conditions - voltages are with respect to v ss unless otherwise stated characteristics sym. min. typ. max. units test conditions 1 supply voltage v dd 2.7 3 3.6 v 2 cmos input voltage (high) v ihc 0.9*v dd v dd v 3 cmos input voltage (low) v ilc v ss 0.1*v dd v 4 operating temperature t a - 40 + 85 c power characteristics characteristics sym. min. typ. max. units test conditions 1 static supply current (clock disabled, all functions off, pdfdi/pddr=1, pwrst=0) i ddc1 220 a outputs unloaded, input signals static, not loaded 2 dynamic supply current: total all functions enabled i ddft 6 10 ma see note 1.
mt91l60/61 data sheet 21 zarlink semiconductor inc. ? dc electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note 1 - magnitude measurement, ignore signs. ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 input high voltage cmos inputs v ihc 0.7*vdd v 2 input low voltage cmos inputs v ilc 0. 3*vdd v 3 vbias voltage output v bias v dd /2 v max. load = 20k ? 4 vref voltage output v ref v dd /2-1.1 v no load 5 input leakage current i iz 0.1 10 ma v in =v dd to v ss 6 positive going threshold voltage (pwrst only) negative going threshold voltage (pwrst only) hysteresis v t+ v t- 2.2 0.65 0.7 v v v vdd = 3v 7 output high current i oh 1.0 ma v oh = 0.9*v dd see note 1 8 output low current i ol 2.5 ma v ol = 0.1*v dd see note 1 9 output leakage current i oz 0.01 10 ma v out = v dd and v ss 10 output capacitance c o 15 pf 11 input capacitance c i 10 pf clockin tolerance characteristics ? (st-bus mode) characteristics min. typ. ? max. units test conditions 1c4i frequency 4095.6 4096 4096.4 khz (i.e., 100 ppm)
mt91l60/61 data sheet 22 zarlink semiconductor inc. ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: txinc, refer to control register 1, address 00h. ac characteristics ? for a/d (transmit) path - 0dbm0 = a lo3.17 - 3.17 db = 1.027 v rms for -law and 0dbm0 = a lo3.14 - 3.14 db = 1.067 v rms for a-law, at the codec. (v ref = 0.4 v and v bias =1.5 volts.) characteristics sym. min. typ. ? max. units test conditions 1 analog input equivalent to overload decision a li3.17 a li3.14 4.246 4.4 vp-p vp-p -law a-law both at codec 2 absolute half-channel gain m to dout g ax1 g ax2 5.4 14.7 6.0 15.3 6.6 15.9 db db transmit filter gain=0 db setting. txinc = 0* txinc = 1* @1020 hz tolerance at all other transmit filter settings (1 to 7 db) -0.2 0.1 +0.2 db 3 gain tracking vs. input level itu-t g.714 method 2 g tx -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db 3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 4 signal to total distortion vs. input level. itu-t g.714 method 2 d qx 35 29 24 db db db 0 to -30 dbm0 -40 dbm0 -45 dbm0 5 transmit idle channel noise n cx n px 13 -70.5 16 -69 dbrnc0 dbm0p -law a-law 6 gain relative to gain at 1020 hz <50 hz 60 hz 200 hz 300 - 3000 hz 3000-3300 hz 3300 hz 3400 hz 4000 hz 4600 hz >4600 hz g rx -0.25 -0.9 -0.9 -1.2 -45 -0.2 -0.6 -23 -41 -25 -30 0.0 0.25 0.25 0.25 0.25 -12.5 -25 -25 db db db db db db db db db db 7 absolute delay d ax 360 ms at frequency of minimum delay 8 group delay relative to d ax d dx 750 380 130 750 ms ms ms ms 500-600 hz 600 - 1000 hz 1000 - 2600 hz 2600 - 2800 hz 9 power supply rejection f=1020 hz pssr 30 50 db 100 mv peak signal on v dd -law
mt91l60/61 data sheet 23 zarlink semiconductor inc. ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: rxinc, refer to control register 1, address 00h. ac characteristics ? for d/a (receive) path - 0 dbm0 = a lo3.17 - 3.17 db = 1.027 v rms for -law and 0dbm0 = a lo3.14 - 3.14 db = 1.067 v rms for a-law, at the codec. (v ref = 0.4 v and v bias =1.5 volts.) characteristics sym. min. typ. ? max. units test conditions 1 analog output at the codec full scale a lo3.17 a lo3.14 4.183 4.331 vp-p vp-p -law a-law 2 absolute half-channel gain. din to hspkr g ar1 g ar2 g ar3 g ar4 -0.6 -6.6 -6.6 -12.6 0 -6 -6 -12 0.6 -5.4 -5.4 -11.4 db db db db drgain=0, rxinc =1* drgain=0, rxinc =0* drgain=1, rxinc =1* drgain=1, rxinc =0* @ 1020 hz tolerance at all other receive filter settings (-1 to -7 db) -0.2 0.1 +0.2 db 3 gain tracking vs. input level itu-t g.714 method 2 g tr -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db 3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 4 signal to total distortion vs. input level. itu-t g.714 method 2 g qr 35 29 24 db db db 0 to -30 dbm0 -40 dbm0 -45 dbm0 5 receive idle channel noise n cr n pr 11.5 -80 14 -77 dbrnc0 dbm0p -law a-law 6 gain relative to gain at 1020 hz 200 hz 300 - 3000 hz 3000 - 3300 hz 3300 hz 3400 hz 4000 hz 4600 hz >4600 hz g rr -0.25 -0.90 -0.9 -0.9 -0.1 -0.5 -23 -41 0.25 0.25 0.25 0.25 0.25 -12.5 -25 -25 db db db db db db db db 7 absolute delay d ar 240 ms at frequency of min. delay 8 group delay relative to d ar d dr 750 380 130 750 ms ms ms ms 500-600 hz 600 - 1000 hz 1000 - 2600 hz 2600 - 2800 hz 9 crosstalk d/a to a/d a/d to d/a ct rt ct tr -90 -90 -74 -80 db db itu-t g.714.16
mt91l60/61 data sheet 24 zarlink semiconductor inc. ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: rxinc, refer to control register 1, address 00h. ? electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: rxinc, refer to control register 1, address 00h. ? electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: txinc, refer to control register 1, address 00h. ac electrical characteristics ? for side-tone path characteristics sym. min. typ. ? max. units test conditions 1 absolute path gain gain adjust = 0 db g as1 g as2 -17.1 -11.1 -16.5 -10.5 -15.9 -9.9 db db rxinc = 0* rxinc = 1* m inputs to hspkr outputs 1000 hz at stg2=1 2 tolerance of other side-tone settings (-9.96 to 9.96 db) relative to output at 0 db setting -0.5 +/-0.2 +0.5 db electrical ch aracteristics ? for analog outputs characteristics sym. min. typ. ? max. units test conditions 1 earpiece load impedance e zl 260 300 ohms across hspkr 2 allowable earpiece capacitive load e cl 300 pf each pin: hspkr+, hspkr- 3 earpiece harmonic distortion e d 0.5 % 300 ohms load across hspkr (tol-15%), vo 693mv rms , rxinc=1*, rx gain=0 db electrical characteristics ? for analog inputs characteristics sym. min. typ. ? max. units test conditions 1 maximum input voltage without overloading codec across m+/m- v iolh 2.128 0.756 vp-p vp-p txinc = 0, a/ = 0* txinc = 1, a/ = 1* tx filter gain=0 db setting 2 input impedance z i 50 kw m+/m- to v ssa
mt91l60/61 data sheet 25 zarlink semiconductor inc. ? timing is over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: all conditions data-data, data-hiz, hiz-data. figure 11 - st-bus timing diagram ac electrical characteristics ? - st-bus timing (see figure 11) characteristics sym. min. typ. ? max. units test conditions 1c4i clock period t c4p 244 ns 2c4i clock high period t c4h 122 ns 3c4i clock low period t c4l 122 ns 4c4i clock transition time t t 20 ns 5f0i frame pulse setup time t f0is 50 ns 6f0i frame pulse hold time t f0ih 50 ns 7 delayed frame pulse delay after c4i rising t f0ods 55 ns 8 delayed frame pulse hold time from c4i rising t f0odh 50 ns 9dsto delay t dstod 125 ns c l = 30 pf, 1 k ? load.* 10 dsti setup time t dstis 20 ns 11 dsti hold time t dstih 50 ns dsto dsti 70% 30% 70% 30% 70% 30% 70% 30% note: levels refer to%v dd t t t t t c4l t c4h t c4p 1 bit cell t dstis t dstih t f0is t f0ih t t t dstod t t c4i f0i 70% 30% f0od t f0ods t f0odh 64 clock periods
mt91l60/61 data sheet 26 zarlink semiconductor inc. ? timing is over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1: not production tested, guaranteed by design. ac electrical characteristics ? - ssi bus synchronous timing (see figure 12) characteristics sym. min. typ. ? max. units test conditions 1 bcl clock period t bcl 244 1953 ns bcl=4096 khz to 512 khz 2 bcl pulse width high t bclh 115 122 ns bcl=4096 khz 3 bcl pulse width low t bcll 122 ns bcl=4096 khz 4 bcl rise/fall time t r /t f 20 ns note 1 5 strobe pulse width t enw 8 x t bcl ns note 1 6 delayed strobe pulse width t enwd 8 x t bcl ns note 1 7 strobe setup time before bcl falling t sss 70 t bcl -80 ns 8 strobe hold time after bcl falling t ssh 80 t bcl -80 ns 9 delayed strobe pulse delay after bcl rising t dstbr 55 ns note 1 10 delayed strobe pulse hold time after bcl rising t dstbf 55 ns note 1 11 dout high impedance to active low from strobe rising t dozl 55 ns c l =50 pf, r l =1 k 12 dout high impedance to active high from strobe rising t dozh 55 ns c l =50 pf, r l =1 k 13 dout active low to high impedance from strobe falling t dolz 90 ns c l =50 pf, r l =1 k 14 dout active high to high impedance from strobe falling t dohz 90 ns c l =50 pf, r l =1 k 15 dout delay (high and low) from bcl rising t dd 80 ns c l =50 pf, r l =1 k 16 din setup time before bcl falling t dis 10 ns 17 din hold time from bcl falling t dih 50 ns
mt91l60/61 data sheet 27 zarlink semiconductor inc. figure 12 - ssi synchronous timing diagram (bcl) din dout stb 70% 30% 70% 30% 70% 30% 70% 30% t bclh t r t f t bcll t dis t dih t dozl t dd t bcl t dozh t sss t enw t ssh t dolz t dohz note: levels refer to% v dd (cmos i/o) clockin 70% 30% stbd t enwd t dstbr t dstbf
mt91l60/61 data sheet 28 zarlink semiconductor inc. ? timing is over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1: not production tested, guaranteed by design. figure 13 - ssi asynchronous timing diagram ac electrical characteristics ? - ssi bus asynchronous timing (note 1) (see figure 13) characteristics sym. min. typ. ? max. units test conditions 1 bit cell period t data 7812 3906 ns ns bcl=128 khz bcl=256 khz 2 frame jitter t j 600 ns 3 bit 1 dout delay from stb going high t dda1 t j +600 ns c l =50 pf, r l =1 k 4 bit 2 dout delay from stb going high t dda2 600+ t data -t j 600+ t data 600 + t data +t j ns c l =50 pf, r l =1 k 5 bit n dout delay from stb going high t ddan 600 + (n-1) x t data -t j 600 + (n-1) x t data 600 + (n-1) x t data +t j ns c l =50 pf, r l =1 k n=3 to 8 6 bit 1 data boundary t data1 t data -t j t data +t j ns 7 din bit n data setup time from stb rising t su t data \2 +500ns-t j +(n-1) x t data ns n=1-8 8 din data hold time from stb rising t ho t data \2 +500ns+t j +(n-1) x t data ns din dout stb 70% 30% 70% 30% 70% 30% t j t dda1 note: levels refer to% v dd (cmos i/o) t dha1 t data1 t dda2 t data bit 1 bit 2 bit 3 d1 d2 d3 t ho t su t data /2 t data t data
mt91l60/61 data sheet 29 zarlink semiconductor inc. ? timing is over recommended temperature range & recommended power supply voltages. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note: all conditions data-data, data-hiz, hiz-data. figure 14 - microport timing ac electrical characteristics ? - microport timing (see figure 14) characteristics sym. min. typ. ? max. units test conditions 1 input data setup t ids 100 ns 2 input data hold t idh 30 ns 3 output data delay t odd 120 ns c l = 50pf, r l = 1 k * 4 serial clock period t cyc 500 1000 ns 5 sclk pulse width high t ch 250 500 ns 6 sclk pulse width low t cl 250 500 ns 7cs setup-intel t cssi 200 ns 8cs setup-motorola t cssm 100 ns 9cs hold t csh 100 ns 10 cs to output high impedance t ohz 120 ns c l = 50pf, r l = 1 k hiz hiz data input data input data output data output 2.0 v 0.8 v 90% 10% 90% 10% 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v t ids t idh t cyc t odd t cssi t ch t ohz 2.0 v 0.8 v t cssm t idh t ids 2.0 v 0.8 v t cyc t odd t csh note: % refers to% v dd sclk sclk intel mode = 0 motorola mode = 00 cs t cl t ch t cl

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